8284125: AArch64: Remove partial masked operations for SVE

Currently there are match rules named as xxx_masked_partial, which are
expected to work on masked vector operations when the vector size is not
the full size of hardware vector reg width, i.e. partial vector. Those
rules will make sure the given masked (predicate) high bits are cleared
with vector width. Actually, for those masked rules with predicate
input, if we can guarantee the input predicate high bits are already
cleared with vector width, we don't need to re-do the clear work before
use. Currently, there are only 4 nodes on AArch64 backend which
initializes (defines) predicate registers:

  1.MaskAllNode
  2.VectorLoadMaskNode
  3.VectorMaskGen
  4.VectorMaskCmp

We can ensure that the predicate register will be well initialized with
proper vector size, so that most of the masked partial rules with a mask
input could be removed.

[TEST]
vector api jtreg tests passed on my SVE testing system.

Change-Id: Iee3d7c5952f7634458222cad9eec1cc661818b8e